DocumentCode
3371299
Title
Multi-level parallelism analysis of face detection on a shared memory multi-core system
Author
Chiang, Chih-Hsuan ; Kao, Chih-Heng ; Li, Guan-Ru ; Lai, Bo-Cheng Charles
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2011
fDate
25-28 April 2011
Firstpage
1
Lastpage
4
Abstract
Face detection is one of the fundamental technologies for the future smart objects. However, its computation intensive property thwarts the practice of a real-time application on an embedded device. Parallel processing and many-core architecture have become a mainstream to achieve high performance in the future computing systems. The parallelism of an application needs to be exposed before being exploited by the parallel architecture. This paper performs a comprehensive analysis of the parallelism of a face detection algorithm at different algorithmic levels. This paper has demonstrated that each parallelism level has its own potential to enhance performance, but also imposes different limiting factors to the overall performance. Based on the analysis results and design experience, this paper proposes a multi-staged mixed-level parallelization scheme to retain the performance scalability and avoid the limiting factors. With this scheme, we are able to achieve up to 37.5x performance enhancement on a 64-core system.
Keywords
face recognition; parallel architectures; shared memory systems; embedded device; face detection; many-core architecture; multistaged mixed-level parallelization; parallel architecture; parallel processing; shared memory multicore system; Algorithm design and analysis; Classification algorithms; Computer architecture; Face; Face detection; Instruction sets; Parallel processing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Conference_Location
Hsinchu
ISSN
Pending
Print_ISBN
978-1-4244-8500-0
Type
conf
DOI
10.1109/VDAT.2011.5783540
Filename
5783540
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