Hardware complexity metrics for high level synthesis of software functions

High level synthesis using C/C++ code of applications is rapidly gaining ground. Code profiling has traditionally been used to select code blocks to implement in hardware by using ASICs, FPGAs or other programmable logic. We present a set of new hardware complexity metrics to reason about the suitability of a software function for its implementation by hardware synthesis. Our proposed metrics bring in the hardware aware perspective in the design process and overcome certain specific but important limitations inherent in code profiling based analysis. The metrics defined in the current work also help in design management and are applicable to innovative and future applications which are not fully developed to enable their code profiling.