Programmable AND-CFAR signal detector design and its FPGA prototyping for FMCW radar systems

This paper presents the digital signal processor design for constant-false-alarm-rate (CFAR) signal detection in a frequency-modulated-continuous-waveform (FMCW) radar system. It is capable of identifying the beat signal from the spectrum so as to calculate the distance between the radar and the ground. The proposed CFAR signal detection design is an enhancement of the basic AND-CFAR architecture, which combines the algorithms of cell averaging (CA) and order statistics (OS) and provides a better signal detection performance. To achieve high throughput detection, an incremental calculation scheme was adopted to simplify the computing complexity. For the cell averaging module, only four additions are required regardless of the reference window size. For the order statistics module, the sorting process is cleverly accomplished in every clock cycle via one removal and one insertion operations. The design is also adaptable to different ordering value k and scaling factor T. Implementation results on FPGA devices suggest the design consumes a very small amount of hardware resources (857 slices only) and is capable of working at a maximum frequency equal to 121.33MHz.