High-performance logarithmic converters using novel two-region bit-level manipulation schemes

In this paper, we propose a high-performance logarithmic converter using novel two-region bit-level manipulation schemes. The proposed technique provides an area-time-efficient hardware implementation, since it avoids the need of a ROM by using simple arithmetic operations instead. Accuracy analysis shows that the proposed converter can achieve an error range and percent error range of only 0.0319 and 2.337%, respectively, which outperforms the previously proposed methods with one-region and multi-region shift-and-add schemes. We have synthesized the proposed logarithmic converter using 0.18 μm CMOS technology, and have estimated the area and time complexities. The proposed design offers 9.4% less area-delay product, compared to the best of the existing two-region logarithmic conversion method with nearly 44% less error range with comparable area consumptions. It involves 62.7, and 60.1% less area-delay product than the existing four-region and six-region logarithmic conversion methods, respectively. The proposed converter could be used to ease the area- and time-consuming multiplications, divisions and non-linear function evaluations for real-time digital signal processing and soft-computing applications in dedicated hardware.