DocumentCode
3371588
Title
A low-power vdd-management technique for high-speed domino circuits
Author
Tsai, Yu-Tzu ; Huang, Hsiang-Hui ; Hsu, Sheng-Wei ; Cheng, Ching-Hwa ; Guo, Jiun-In
Author_Institution
Dept. of ECE, Feng-Chia Univ., Taichung, Taiwan
fYear
2011
fDate
25-28 April 2011
Firstpage
1
Lastpage
4
Abstract
A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.
Keywords
CMOS integrated circuits; low-power electronics; power supplies to apparatus; CMOS technology; charge-sharing voltage; dynamic power consumption; high-speed domino circuits; low power voltage management technique; low-power VDD-management technique; size 0.13 mum; static power consumption; test chip; CMOS integrated circuits; Circuit synthesis; Clocks; Delay; Design automation; Logic gates; Power demand;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Conference_Location
Hsinchu
ISSN
Pending
Print_ISBN
978-1-4244-8500-0
Type
conf
DOI
10.1109/VDAT.2011.5783556
Filename
5783556
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