Title :
Efficient weighted modulo 2n+1 adders by partitioned parallel-prefix computation and enhanced circular carry generation
Author :
Juang, Tso-Bing ; Meher, Pramod Kumar ; Chiu, Chin-Chieh
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Pingtung Inst. of Commerce, Pingtung, Taiwan
Abstract :
In this paper, we propose a low complexity design of weighted modulo 2n+1 adder, derived by decomposition of parallel-prefix computation into several blocks of smaller input bit-widths. Besides, we have proposed a novel enhanced circular carry generation (ECCG) unit to process the carry-bits produced by all the parallel-prefix computation units (of small input bit-widths) to obtain the final modulo sum efficiently in terms of area-delay product. We have implemented the proposed adders using 0.13 μm CMOS technology; and from the synthesis results we find that our proposed adder outperforms the previously reported weighted modulo 2n+1 adders. It offers a saving of area-delay product up to 49% over the existing methods.
Keywords :
CMOS logic circuits; adders; CMOS technology; ECCG unit; area-delay product; enhanced circular carry generation unit; input bitwidth; partitioned parallel-prefix computation; size 0.13 mum; weighted modulo 2n+1 adder; Adders; Computational efficiency; Computer architecture; Computer science; Finite impulse response filter; Very large scale integration; Modulo 2n+1 adder; VLSI design; residue number system (RNS);
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-8500-0
DOI :
10.1109/VDAT.2011.5783558
