Title :
On the bus arbitration for MPEG 2 video decoder
Author :
Lin, Chia-Hsing ; Jen, Chein-Wei
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
31 May-2 Jun 1995
Abstract :
A bus arbitration scheme for the MPEG-2 video decoder VLSI developed by NCTU is proposed in this paper. Compared to the traditional pure stochastic bus scheduling scheme, the internal buffer requirement and bus arbitration overheads are reduced due to the deterministic nature of this strategy. This bus arbitration scheme has been verified using a Verilog simulator and will be implemented in the NCTU MPEG-2 decoder
Keywords :
VLSI; decoding; digital signal processing chips; system buses; video coding; MPEG 2 video decoder; NCTU; VLSI; Verilog simulation; bus arbitration; deterministic scheduling; internal buffer; Bandwidth; Control systems; Costs; Decoding; Displays; Hardware design languages; Pipelines; Random access memory; Stochastic processes; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2773-X
DOI :
10.1109/VTSA.1995.524663
