Title :
A temperature compensated array of CMOS floating-gate analog memory
Author :
Huang, Chenling ; Chakrabartty, Shantanu
Author_Institution :
Dept. of Electr. & Comput. Eng., Michigan State Univ., East Lansing, MI, USA
fDate :
May 30 2010-June 2 2010
Abstract :
Floating-gate transistors have been extensively used as analog memory elements in adaptive learning and neural systems. However, conventional techniques for storing and programming sub-threshold currents on floating-gate transistors are sensitive to temperature variations thus limiting their applicability to controlled environments. In this paper, we propose a temperature compensated floating-gate array which can be used to store and program currents down to nanoampere level. The core of the proposed current memory is a dual-channel floating-gate transistor based current reference circuit which uses a linear resistor in translinear loop. As a result the stored current is linearly proportional to the charge on the floating-gate and hence can be precisely programmed. The paper presents results from a prototype fabricated in a 0.5-μm CMOS process which validates the functionality of the proposed current memory cell.
Keywords :
CMOS analogue integrated circuits; CMOS memory circuits; neural nets; resistors; adaptive learning; analog memory elements; current memory cell; floating gate analog memory; floating gate transistor; linear resistor; nanoampere level; neural systems; size 0.5 mum; temperature compensated CMOS array; translinear loop; Analog memory; CMOS process; Circuits; Computer architecture; Computer errors; Nonvolatile memory; Prototypes; Resistors; Signal processing; Temperature sensors;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5536998