Title :
A single-chip lossless data compressor
Author :
Wei, Belle W Y ; Chang, James L. ; Leong, V.I.
Author_Institution :
Dept. of Electr. Eng., San Jose State Univ., CA, USA
fDate :
31 May-2 Jun 1995
Abstract :
This paper describes a single-chip compressor implementing a combined LZSS and Huffman compression algorithm. The chip uses a 512-byte on-chip CAM/SRAM for storing the most recent characters which the incoming string is compared against and referenced to. The reference entries are then Huffman coded using a transposition implementation. The chip in 1.2 μm CMOS is 0.9 cm2 with a clock speed of 40 ns. With a compression ratio of above 2.1, it performs compression/decompression at a rate of 32 bytes per 33 clock cycles
Keywords :
CMOS digital integrated circuits; Huffman codes; data compression; digital signal processing chips; 1.2 micron; 40 ns; 512 byte; CAM/SRAM; CMOS chip; Huffman coding; LZSS algorithm; single-chip lossless data compressor; transposition; Algorithm design and analysis; Clocks; Codecs; Compression algorithms; Data engineering; Decoding; Dictionaries; Educational institutions; Huffman coding; Testing;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2773-X
DOI :
10.1109/VTSA.1995.524665
