Limitations on oxide thicknesses in flash EEPROM applications

Oxides used in EEPROMs have severe limitations placed on leakage currents due to long data retention time requirements. During write/erase (W/E) cycling, traps, responsible for both decreased tunneling currents and increased stress-induced leakage currents (SILCs), are generated inside the tunnel oxides. The decreased tunneling currents impose endurance limitations. The increased SILCs are partially responsible for data retention limitations. Since oxide thicknesses are continually being reduced, it is important to characterize these SILCs in thinner oxides, to relate these leakages to the trap generation inside the oxides, to separate the transient trap charging/discharging currents from the dc currents, and to determine the limitations placed on oxide reliability by oxide thickness reductions in flash EEPROM applications. The SILCs have been measured on oxides in the 4 nm to 13 nm thickness range. Trap generation and oxide charges were also measured. The SILCs were correlated with the oxide thicknesses and trap generations. Limitations on oxide thicknesses determined by data retention limits have been estimated.