DocumentCode :
3372150
Title :
Output-pattern directed decomposition for low power design
Author :
Hu, Chi-Wei ; Hwang, TingTing
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
5
fYear :
2004
fDate :
23-26 May 2004
Abstract :
It is observed that in some circuits, highly active output-patterns fall into a small set. Based on this observation, we propose an output directed decomposition architecture and an algorithm to synthesize the decomposed logic. The results on several MCNC benchmark circuits shows that the proposed method can achieve 34.1% reduction is power as compared to circuits without decomposition.
Keywords :
logic partitioning; low-power electronics; MCNC benchmark circuits; decomposed logic; low power design; output-pattern directed decomposition; power reduction; Circuit synthesis; Codecs; Combinational circuits; Computer architecture; Computer science; Energy consumption; Latches; Logic; Minimization methods; Partitioning algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
Type :
conf
DOI :
10.1109/ISCAS.2004.1329481
Filename :
1329481
Link To Document :
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