Title :
Trapped hole enhanced stress induced leakage currents in NAND EEPROM tunnel oxides
Author :
Hemink, G.J. ; Shimizu, K. ; Aritome, S. ; Shirota, R.
Author_Institution :
ULSI Res. Lab., Toshiba Corp., Kawasaki, Japan
fDate :
April 30 1996-May 2 1996
Abstract :
The stress induced tunnel oxide leakage current occurring in NAND EEPROM memory cells after a large number of WRITE/ERASE (W/E) cycles has been investigated for different W/E pulses. A model for the stress induced leakage current is proposed in which the presence of both holes and neutral oxide traps are a necessary condition for the stress induced leakage current to occur.
Keywords :
EPROM; MOS memory circuits; NAND circuits; hole traps; integrated circuit reliability; integrated circuit testing; leakage currents; NAND EEPROM; hole traps; memory cells; neutral oxide traps; stress induced leakage currents; tunnel oxides; write/erase cycles; Capacitance; Current density; Current measurement; EPROM; Equations; Leakage current; Nonvolatile memory; Stress; Tunneling; Voltage control;
Conference_Titel :
Reliability Physics Symposium, 1996. 34th Annual Proceedings., IEEE International
Conference_Location :
Dallas, TX, USA
Print_ISBN :
0-7803-2753-5
DOI :
10.1109/RELPHY.1996.492070
