fDate :
April 27 2008-May 1 2008
Abstract :
The following topics were dealt with: high speed communication systems testing; compaction for testing; ATE data volume; scan chains testing; device degradation; infant mortality; memory diagnosis; automatic test development; nanometer CMOS; low power scan testing; analog circuit testing; RF circuit testing; transition faults testing; design for yield; design for manufacturability; delay test; error tolerance; STIL utilization; nanoelectronics; mixed signal circuit testing; complex failure mechanisms; debug and diagnosis; semiconductor test; IP fault localization; reliability mitigation and biomedical devices.
Keywords :
CMOS integrated circuits; analogue integrated circuits; automatic test pattern generation; biomedical electronics; design for manufacture; fault tolerance; integrated circuit reliability; integrated circuit testing; integrated memory circuits; nanoelectronics; semiconductor device testing; very high speed integrated circuits; ATE data volume; RF circuit testing; STIL utilization; analog circuit testing; automatic test development; biomedical devices; complex failure mechanisms; delay test; design-for-manufacturability; design-for-yield; device degradation; error tolerance; fault localization; high speed communication systems; infant mortality; low power scan testing; memory diagnosis; mixed signal circuit testing; nanoelectronics; nanometer CMOS; reliability mitigation; scan chains; semiconductor test; testing compaction; transition faults;
Conference_Titel :
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location :
San Diego, CA
Print_ISBN :
978-0-7695-3123-6
DOI :
10.1109/VTS.2008.91
