A systematic approach for analyzing fast addition algorithms using counter tree diagrams

This work presents a unified representation of fast addition algorithms based on counter tree diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include redundant-binary (RB) adders, signed-digit (SD) adders, positive-digit (PD) adders, carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. In this paper, we focus on an application of CTDs to the analysis of two-operand RB adders with limited carry propagation. The analysis result shows that there exists possible two types 3-stage CTDs for the RB adders. From this result, we can confirm that well-known RB adders are classified into one of the two types.