Title :
High performance DDR architecture in Intel® Core™ processors using 32nm CMOS high-K metal-gate process
Author :
Mosalikanti, Praveen ; Mozak, Chris ; Kurd, Nasser
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
This paper describes the DDR architecture in Intel® Core™ processors operating up to 1333MT/s and designed in 32nm process technology. The architecture uses adaptive techniques to achieve very low clock jitter (40% margin to spec), data scrambling to reduce simultaneous switching noise and novel training algorithms to improve I/O margins in the presence of crosstalk. A fast wakeup technique allows shutting down the receive path for finer grain power management, reducing standby power by 15%.
Keywords :
CMOS digital integrated circuits; microprocessor chips; phase locked loops; CMOS high-K metal-gate process; I/O margin improvement; Intel core processor; PLL; clock jitter; grain power management; high performance DDR architecture; size 32 nm; switching noise; training algorithm; Clocks; Crosstalk; Delay; Logic gates; Noise; Phase locked loops; Quantum cascade lasers;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-8500-0
DOI :
10.1109/VDAT.2011.5783599
