A SPT treatment to the bit serial realization of the sign-LMS based adaptive filter

This paper presents a bit serial realization of the sign-LMS based adaptive filter which enjoys multiplier free weight update loop. To reduce the complexity of the multipliers that arise in the filtering process, the filter weights are represented in the so-called canonic SPT form which guarantees presence of at least one zero between every two non-zero power-of-two terms. As the filter weights are not fixed but updated in time, it is essential to ensure that the canonic SPT format is retained in the updated filter coefficients. For this, a bit serial adder is proposed that takes as input two numbers in canonic SPT and produces an output also in canonic SPT. It is further shown how the canonic SPT property of the input can be used to reduce the complexity of the adder. For the filtering part, a bit serial multiplier is developed that takes one input (i.e., data bits) in 2´s complement form and the other input (i.e., weight bits) in canonic SPT, producing the result in 2´s complement. The multiplication can not, however, be realized using a few fixed shift and add operations, since the position of the non-zero SPT terms in the canonic SPT expression of each coefficient changes with time. The proposed multiplier instead multiplies the 2´s complement number with pairs of consecutive SPT bits of the other number. The resulting partial products can be realized using simple AND-OR logic.