Fast multilevel floorplanning for large scale modules

With the advance of deep sub-micron, current methods are not effective to obtain acceptable layout for large scale modules. Hence, it is important to provide designers of SoC with a powerful floorplanner. In traditional approaches, it is common to simultaneously utilize clustering and declustering technologies, i.e. multiple phases to refine the solution quality. We propose a top-down multilevel genetic floorplanning algorithm to handle the floorplanning and packing for large scale modules. The algorithm is simple and only needs the clustering phase. Experimental results show significantly better running time and promising solutions in comparison with other state-of-the-art research works.