ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

Author

Zhan, Rouying ; Feng, Haigang ; Xie, Haolu ; Wang, Albert

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA

Volume

5

fYear

2004

fDate

23-26 May 2004

Abstract

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a smart parametric checking mechanism and the first intelligent CAD tool, entitled ESDInspector, developed for full-chip ESD protection circuitry design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35μm BiCMOS.

Keywords

BiCMOS integrated circuits; circuit CAD; electrostatic discharge; formal verification; integrated circuit layout; integrated circuit testing; 0.35 micron; BiCMOS; ESDInspector; design verification tool; electrostatic discharging protection; integrated circuit design; intelligent CAD tool; layout-level ESD protection circuitry; on-chip ESD; smart-parametric checking mechanism; BiCMOS integrated circuits; Breakdown voltage; Circuit synthesis; Design automation; Electrostatic discharge; Protection; Radio frequency; Radiofrequency integrated circuits; Silicon; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329501

Filename

1329501