DocumentCode
3372649
Title
How Many Test Patterns are Useless?
Author
Ferhani, François-Fabien ; Saxena, Nirmal R. ; McCluskey, Edward J. ; Nigh, Phil
Author_Institution
Center for Reliable Comput., Stanford Univ., Stanford, CA
fYear
2008
fDate
April 27 2008-May 1 2008
Firstpage
23
Lastpage
28
Abstract
Studies by previous researchers using production test data reported that not all the production test patterns applied detected defective chips. Researchers found that 70% to 90% of their production test patterns seemed useless because these patterns detected no defective chips and they could therefore be removed without impacting test quality. Previous researchers qualitatively explained this finding by a lack of correlation between test metrics and defect coverage. Notwithstanding the lack of correlation between test metrics and defect coverage, in this paper we develop a simple statistical model that relates the expected number of useless patterns to the production yield, the defect coverage characteristics, and the number of tested chips. This model demonstrates that for practical values of production yield, defect coverage and number of chips tested, a significant fraction of test patterns will be useless. We validated this statistical model by comparing its results with actual production testing data.
Keywords
automatic test pattern generation; integrated circuit yield; production testing; statistical analysis; defect coverage; defective chips; production test patterns; production yield; simple statistical model; test metrics; test quality; Automatic test pattern generation; Automatic testing; Economic forecasting; Fault detection; Predictive models; Production; Rivers; Very large scale integration; Yield estimation; Test Economics; Test Patterns; Truncation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location
San Diego, CA
ISSN
1093-0167
Print_ISBN
978-0-7695-3123-6
Type
conf
DOI
10.1109/VTS.2008.27
Filename
4511691
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