Abstract :
Zero defect (ZD) objective is met today with a comprehensive and inter-disciplinary ZD Program that spans across the entire IC development flow. DFT (design for testability) is a critical component of the ZD program and has the potential to increase its utility. While scan and memory BIST are being used effectively, the DFT methodologies around analog, RF, MEMs, high-speed 10 and mixed-signal logic are not well established. Advances in low power design - such as dynamic voltage and frequency scaling, power domains and the use of sophisticated clock-gating structures - have created new challenges for testing these low-power structures as well as rest of the IC. Finally, for 45 nm and below, yield is a big issue. One of the key requirements for zero defects is high Yield. DFT methods have the potential to accelerate yield learning for new processes so that they can achieve ZD qualification in a timely manner. This presentation will describe the DFT opportunities, what has been done and a collaborative framework for future work.
