Design Synthesis and Performance Measurement of Pipelined Flash ADC for SoC Applications

Author

Wang, Mingzhen ; Henry Chen, Chien-In

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH

Volume

1

fYear

2005

fDate

16-19 May 2005

Firstpage

19

Lastpage

24

Abstract

This paper presents a design synthesis and performance measurement of a 4-bit pipelined flash analog-to-digital converter (ADC). The preliminary results show the ADC in 130 nanometer CMOS. CMOS technology has superior performance of sampling rate of 2.5 GHz for input signal bandwidth of 1 GHz. For the purpose of design reuse, a general architecture and synthesis flow of the ADC is proposed. One of such work is about solution of a long-standing open problem on the design synthesis of high-performance ADC

Keywords

CMOS digital integrated circuits; analogue-digital conversion; integrated circuit design; system-on-chip; 1 GHz; 130 nm; 2.5 GHz; 4 bit; CMOS technology; SoC applications; analog-to-digital converter; pipelined flash ADC; system-on-chip; CMOS technology; Clocks; Delay; Digital signal processing chips; Integrated circuit synthesis; Measurement; Radio frequency; Sampling methods; Signal synthesis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 2005. IMTC 2005. Proceedings of the IEEE

Conference_Location

Ottawa, Ont.

Print_ISBN

0-7803-8879-8

Type

conf

DOI

10.1109/IMTC.2005.1604060

Filename

1604060