Asymmetrical ground gating for low leakage and data robust sleep mode in memory banks

Author

Jiao, Hailong ; Kursun, Volkan

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2011

fDate

25-28 April 2011

Firstpage

1

Lastpage

4

Abstract

A new asymmetrical ground gated 7T SRAM circuit technique is presented in this paper to lower leakage currents and enhance noise immunity in idle memory banks. A novel write assist scheme is proposed to enhance write margin with the new memory circuit. The leakage power consumption is suppressed by up to 4.30× and the data stability is enhanced by up to 4.79× as compared with the previously published ground gated SRAM circuits in a UMC 80 nm CMOS technology. Furthermore, the write margin is increased by up to 59.94% with the new asymmetrical memory circuit as compared to a previously published asymmetrical SRAM ground gating technique.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit noise; leakage currents; memory architecture; CMOS technology; asymmetrical SRAM ground gating technique; asymmetrical ground gated 7T SRAM circuit technique; asymmetrical ground gating; asymmetrical memory circuit; data robust sleep mode; data stability; ground gated SRAM circuits; idle memory banks; leakage currents; leakage power consumption; low leakage; noise immunity; size 80 nm; write assist scheme; write margin; Arrays; CMOS integrated circuits; CMOS technology; Circuit stability; Logic gates; Random access memory; Transistors; MTCMOS; SRAM; data stability; leakage power; noise; write assist scheme; write margin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Conference_Location

Hsinchu

ISSN

Pending

Print_ISBN

978-1-4244-8500-0

Type

conf

DOI

10.1109/VDAT.2011.5783611

Filename

5783611