DocumentCode :
3372737
Title :
Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER)
Author :
Pan, Zhaoliang ; Breuer, Melvin A.
Author_Institution :
Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA
fYear :
2008
fDate :
April 27 2008-May 1 2008
Firstpage :
59
Lastpage :
66
Abstract :
As CMOS scaling continues to decrease and new technologies emerge, feature sizes approach molecular sizes. Due to high defect rates, process variations and quantum effects, manufacturing yields have decreased. To increase the effective yield, error-tolerance, which allows for some defective chips to be employed in systems that can tolerate errors, has been proposed. To support error-tolerance, the acceptability of defective chips must be quantified according to certain measures. A new measure is proposed in this paper, namely significance-based error-rate (SBER). SBER combines two previously studied error-tolerance measures, namely error-significance and error-rate. In this paper we introduce three different ways to quantify the SBER value(s) of a defective chip using built-in self-test (BIST). These techniques cover the following scenarios: (1) multiple copies of a target circuit where at least one copy is non-defective; (2) multiple copies of a target circuit where none are defect free; and (3) single copy of a defective target circuit. For each scenario, the statistical characteristics of the estimation of the SBER value are discussed.
Keywords :
CMOS integrated circuits; built-in self test; error statistics; CMOS scaling; basing acceptable error-tolerant performance; built-in self-test; defective target circuit; error-tolerance; quantum effects; significance-based error-rate (SBER); Application specific integrated circuits; Built-in self-test; CMOS technology; Discrete cosine transforms; Frequency; Image coding; Manufacturing processes; Semiconductor device measurement; Testing; Very large scale integration; SBER; error-rate; error-significance; error-tolerance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location :
San Diego, CA
ISSN :
1093-0167
Print_ISBN :
978-0-7695-3123-6
Type :
conf
DOI :
10.1109/VTS.2008.51
Filename :
4511697
Link To Document :
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