DocumentCode :
3372752
Title :
Diagnosis of Scan Clock Failures
Author :
Lee, King Leong ; Basturkmen, Nadir Z. ; Venkataraman, Srikanth
Author_Institution :
Intel Corp., Penang
fYear :
2008
fDate :
April 27 2008-May 1 2008
Firstpage :
67
Lastpage :
72
Abstract :
In this paper we present a fault diagnosis procedure for defects in the scan clock tree. We first identify the candidate clock tree buffers common to failing chains by backtracing. We then evaluate and rank these candidates by forward tracing and simulation. Experimental results show that the proposed procedure provides accurate diagnosis of scan clock failures.
Keywords :
boundary scan testing; clocks; fault diagnosis; fault trees; integrated circuit testing; logic testing; backtracing; clock tree buffers; fault diagnosis; scan clock failure diagnosis; scan clock tree; Clocks; Decision support systems; Fiber reinforced plastics; Testing; Very large scale integration; diagnosis; scan chain; scan clock;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location :
San Diego, CA
ISSN :
1093-0167
Print_ISBN :
978-0-7695-3123-6
Type :
conf
DOI :
10.1109/VTS.2008.59
Filename :
4511698
Link To Document :
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