• DocumentCode
    3372759
  • Title

    A referenceless all-digital fast frequency acquisition full-rate CDR circuit for USB 2.0 in 65nm CMOS technology

  • Author

    Chung, Ching-Che ; Dai, Wei-Cheng

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Min-Hsiung, Taiwan
  • fYear
    2011
  • fDate
    25-28 April 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    An all-digital fast frequency acquisition full-rate clock and data recovery (CDR) circuit for USB 2.0 applications without a reference clock is presented in this paper. The proposed digitally controlled oscillator (DCO) with an embedded time-to-digital converter (TDC) can recover the frequency of the synchronous data pattern in a very short time. In addition, the whole frequency acquisition can be finished within 31 cycles. A dual mode phase and frequency detector (PFD) is proposed to perform phase and frequency tracking with random data pattern to maintain the frequency and phase of the recovery clock. The proposed CDR circuit can operate at 480MHz for the USB 2.0 high-speed mode. The proposed CDR circuit can tolerance input data jitter up to 150ps with the bit error rate less than 10-12. The proposed CDR circuit is implemented in a standard process 65nm CMOS process, the core area is 150nm × 150nm, and the power consumption is 1.75mW (@480MHz).
  • Keywords
    CMOS integrated circuits; clock and data recovery circuits; clocks; digital phase locked loops; error statistics; jitter; oscillators; CMOS technology; USB 2.0 application; bit error rate; clock and data recovery circuit; data jitter; digitally controlled oscillator; dual mode phase and frequency detector; frequency 480 MHz; frequency acquisition; power 1.75 mW; random data pattern; referenceless all-digital fast frequency acquisition full-rate CDR circuit; size 65 nm; synchronous data pattern; time 150 ps; time-to-digital converter; Clocks; Delay lines; Frequency control; Frequency synchronization; Phase frequency detector; Synchronization; Universal Serial Bus; clock and data recovery; clocks; digital phase locked loops; jitter; oscillator; synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    Pending
  • Print_ISBN
    978-1-4244-8500-0
  • Type

    conf

  • DOI
    10.1109/VDAT.2011.5783614
  • Filename
    5783614