Compact hardware architectures for BLAKE and LAKE hash functions

Author

Li, Jianzhou ; Karri, Ramesh

Author_Institution

Polytech. Inst. of NYU, Brooklyn, NY, USA

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

2107

Lastpage

2110

Abstract

BLAKE, one of SHA-3 candidates, and LAKE hash functions show the characteristic that the block length of the internal state is double its initial and final states, which means more registers are required for the implementation of the hash functions. In this paper, we explore shift register based compact hardware architectures for the two hash functions. This includes the 32-, 64-, and 128-bit datapath architectures for BLAKE. We provide post Place&Route performance results on both ASIC and FPGA platforms. The power consumption for each design is also given. Our results show that BLAKE has comparable performance when compared with the previous standard hash function of Whirlpool and less performance advantages over SHA-256. The results also indicate that BLAKE outperforms LAKE in the hardware implementation.

Keywords

application specific integrated circuits; computer architecture; cryptography; field programmable gate arrays; 128-bit datapath architectures; 32-bit datapath architectures; 64-bit datapath architectures; ASIC platforms; BLAKE hash function; FPGA platforms; LAKE hash function; Place&Route performance; SHA-256; Standard Hash Algorithm; shift register based compact hardware architectures; Application specific integrated circuits; Counting circuits; Energy consumption; Field programmable gate arrays; Hardware; Hydrogen; Lakes; Logic; NIST; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537063

Filename

5537063