Title :
Gate-Oxide Early Life Failure Prediction
Author :
Chen, Tze Wee ; Kim, Kyunglok ; Kim, Young Moon ; Mitra, Subhasish
Author_Institution :
Depts. of Electr. Eng. & Comput. Sci., Stanford Univ., Stanford, CA
fDate :
April 27 2008-May 1 2008
Abstract :
This paper uses 90nm transistor-level experimental data, device modeling, and circuit simulations to establish the following results: 1. A transistor with defective gate- oxide, i.e., a gate-oxide early-life failure (ELF) candidate transistor, produces gradually degraded drive currents over time before it completely loses its transistor characteristics; 2. The above phenomenon results in gradual increase in delays of digital circuit paths containing the ELF candidate transistor before the circuit produces functional failures; 3. Gradual delay shifts caused by ELF candidate transistors are large enough to be detected using inexpensive digital techniques. These results can be utilized to overcome scaled-CMOS reliability challenges through ELF identification during production test or on-line during system operation.
Keywords :
CMOS integrated circuits; circuit simulation; integrated circuit reliability; semiconductor device models; semiconductor device reliability; transistors; CMOS reliability; ELF candidate transistor; circuit simulations; delay shifts; device modeling; digital circuit paths; early life failure prediction; gate-oxide; gradually degraded drive currents; Circuit simulation; Circuit testing; Costs; Degradation; Delay; Digital circuits; Geophysical measurement techniques; Ground penetrating radar; Life testing; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location :
San Diego, CA
Print_ISBN :
978-0-7695-3123-6
DOI :
10.1109/VTS.2008.55