• DocumentCode
    3372943
  • Title

    Broadcast test pattern generation considering skew-insertion and partial-serial scan

  • Author

    Lin, Chien-Ju ; Huang, Jiun-Lang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2011
  • fDate
    25-28 April 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Broadcast scan test patterns suffer low fault detection efficiency due to the broadcast induced test pattern constraints. This paper presents a test pattern generation technique for broadcast scan that´s capable of skew insertion and partial-serial scan - the former alters while the latter partially removes the test pattern constraints due to the broadcast mechanism. The proposed test pattern generator integrates the skew insertion and partial-serial scan capability into its decision-making procedure; this tight hardware/software integration achieves high fault coverage and compression performance without modifying the circuit under test. Experimental results on ISCAS89 and ITC99 benchmark circuits are presented to validate its effectiveness.
  • Keywords
    benchmark testing; circuit testing; fault location; ISCAS89 benchmark circuits; ITC99 benchmark circuits; broadcast test pattern generation; circuit under test; fault detection; partial-serial scan; skew-insertion; Benchmark testing; Circuit faults; Computer architecture; Decision trees; Silicon; Test pattern generators; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    Pending
  • Print_ISBN
    978-1-4244-8500-0
  • Type

    conf

  • DOI
    10.1109/VDAT.2011.5783624
  • Filename
    5783624