Title :
Bounded Adjacent Fill for Low Capture Power Scan Testing
Author :
Chandra, Anshuman ; Kapur, Rohit
Author_Institution :
Synopsys, Inc., Mountain View, CA
fDate :
April 27 2008-May 1 2008
Abstract :
Average and peak power dissipation can be reduced by controlling the switching activity in the scan chains during shift and capture cycles. In particular, minimum transition count or adjacent fill algorithm reduces transitions in the scan chains and has been shown to reduce average power dissipation during shift. In this paper, we show via statistical analysis of industrial circuits that contrary to conventional belief, scan-in and scan-out vectors are highly correlated for adjacent fill vectors. We also show that this correlation can be used to control the switching activity during the capture cycle. We propose a new filling algorithm called bounded adjacent fill that generates test vectors with low shift and capture switching activity and with no impact on pattern count.
Keywords :
integrated circuit testing; statistical analysis; switching circuits; bounded adjacent fill; circuit-under-test; industrial circuits; low capture power scan testing; peak power dissipation; statistical analysis; switching activity; Automatic test pattern generation; Circuit testing; Clocks; Design for testability; Filling; Power dissipation; Statistical analysis; Switching circuits; Test pattern generators; Very large scale integration; capture power; low power; random fill; scan; shift power; test;
Conference_Titel :
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location :
San Diego, CA
Print_ISBN :
978-0-7695-3123-6
DOI :
10.1109/VTS.2008.47