DocumentCode :
3372966
Title :
Built-in self-diagnosis and test time reduction techniques for NAND flash memories
Author :
Chou, Che-Wei ; Hou, Chih-Sheng ; Li, Jin-Fu
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
fYear :
2011
fDate :
25-28 April 2011
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents a low-cost built-in self-diagnosis (BISD) scheme for NAND flash memories, which can support the March-like test algorithms with page-oriented data backgrounds. Two simple test time reduction techniques are also proposed to reduce the test time. Experimental results show that the proposed BISD circuit for a 2M-bit flash memory only needs 1.7K gates. Also, the proposed test time reduction techniques can effectively reduce the test time. Analysis results show that they can reduce the test time to 48.628% of the normal test scheme for a 4G-bit flash memory tested by the March-FT test algorithm with solid data backgrounds.
Keywords :
NAND circuits; built-in self test; flash memories; logic testing; BISD circuit; March-FT test algorithm; March-like test algorithms; NAND flash memories; built-in self-diagnosis; test time reduction techniques; Arrays; Ash; Circuit faults; Flash memory; Logic gates; Random access memory; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Conference_Location :
Hsinchu
ISSN :
Pending
Print_ISBN :
978-1-4244-8500-0
Type :
conf
DOI :
10.1109/VDAT.2011.5783625
Filename :
5783625
Link To Document :
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