Title :
A built-in redundancy-analysis scheme for RAMs with 3D redundancy
Author :
Chang, Yi-Ju ; Huang, Yu-Jen ; Li, Jin-Fu
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Abstract :
Built-in self-repair (BISR) techniques have been widely used to enhance the yield of embedded memories. Built-in redundancy-analysis (BIRA) module is one key component of the BISR circuit. In this paper, we present a BIRA scheme for random access memories (RAMs) with 3D redundancy to improve the yield of RAMs with cluster faults. A RAM with 3D redundancy is equipped with spare rows, spare columns, and spare IOs. The proposed BIRA scheme also can be designed as programmable such that it can serve multiple RAMs and support the multiple-time repair to increase the repair rate further. Experimental results show that the proposed BISR scheme can achieve high repair rate and only incurs 0.4% additional area overhead, compared with an existing BIRA scheme.
Keywords :
random-access storage; redundancy; 3D redundancy; BIRA module; BISR technique; RAM; built-in redundancy-analysis scheme; built-in self-repair technique; embedded memory; random access memory; Built-in self-test; Circuit faults; Maintenance engineering; Random access memory; Redundancy; System-on-a-chip; Three dimensional displays;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-8500-0
DOI :
10.1109/VDAT.2011.5783626
