Scaling issues in lateral power MOSFETs

Author

Darwish, Mohamed ; Huang, John ; Liu, Minxuan ; Shekar, M.S. ; Williams, Richard ; Cornell, Mike

Author_Institution

Siliconix Inc., Santa Clara, CA, USA

fYear

1998

fDate

3-6 Jun 1998

Firstpage

329

Lastpage

332

Abstract

The interconnect limitations and scaling issues for large area lateral multi-cell power MOS transistors as they approach the ULSI realm are investigated. The increased importance of scaling the metal pitch and the number of layers for different MOS technologies is discussed. Furthermore, the voltage drop and current distribution along metal runners for different examples of layout options are examined in order to gain insight into scaling and layout considerations. It is shown that the temperature behaviour of devices with different metal lengths can be used to extract the contribution of the metal interconnects from measured data

Keywords

MOS integrated circuits; ULSI; integrated circuit interconnections; integrated circuit layout; integrated circuit metallisation; integrated circuit modelling; integrated circuit testing; power MOSFET; power integrated circuits; thermal analysis; IC layout; MOS technologies; ULSI; current distribution; device temperature behaviour; interconnect limitations; large area lateral multi-cell power MOS transistors; lateral power MOSFET scaling; lateral power MOSFETs; metal interconnects; metal layer number scaling; metal length; metal pitch scaling; metal runners; voltage drop; Chemical analysis; Current distribution; Fingers; Integrated circuit interconnections; MOS devices; MOSFETs; Plugs; Power dissipation; Ultra large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1998. ISPSD 98. Proceedings of the 10th International Symposium on

Conference_Location

Kyoto

ISSN

1063-6854

Print_ISBN

0-7803-4752-8

Type

conf

DOI

10.1109/ISPSD.1998.702701

Filename

702701