DocumentCode :
3373082
Title :
An AVS/H.264 dual mode video decoder targeted at high definition video applications
Author :
Chien, Cheng-An ; Yang, Yao-Chang ; Yang, Feng-Ming ; Chen, Jia-Wai ; Chang, Hsiu-Cheng ; Guo, Jiun-In
Author_Institution :
Nat. Chung-Cheng Univ., Min-Hsiung, Taiwan
fYear :
2011
fDate :
25-28 April 2011
Firstpage :
1
Lastpage :
4
Abstract :
This paper proposes an AVS/H.264 dual mode video decoder targeted at high definition video applications. The proposed design is compatible to decode H.264-BP/MP/HP and AVS-JP bit-streams with optimization on both system and component levels. On system level, we simplify the control of H.264 MBAFF coding, and reduce buffer size for storing prediction data. On component level, we improve the throughput in bit-stream decoding and integrate AVS/H.264 processing units together to reduce hardware cost. Through the optimization techniques, the proposed design can achieve real-time HD1080 (1920×1088@30Hz) decoding at 150MHz.
Keywords :
decoding; high definition video; video coding; AVS-JP bit-stream; AVS/H.264 dual mode video decoder; H.264 MBAFF coding; H.264-BP/MP/HP decoding; bit-stream decoding; buffer size reduction; frequency 150 MHz; frequency 30 Hz; high definition video; optimization technique; prediction data storing; real-time HD1080 decoding; Complexity theory; Decoding; Encoding; Finite impulse response filter; Hardware; Streaming media; Transforms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Conference_Location :
Hsinchu
ISSN :
Pending
Print_ISBN :
978-1-4244-8500-0
Type :
conf
DOI :
10.1109/VDAT.2011.5783631
Filename :
5783631
Link To Document :
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