DocumentCode
3373163
Title
Automatic Test Pattern Generation for Interconnect Open Defects
Author
Spinner, Stefan ; Polian, Ilia ; Engelke, Piet ; Becker, Bernd ; Keim, Martin ; Cheng, Wu-Tung
Author_Institution
Comput. Archit. Group, Albert-Ludwigs-Univ., Freiburg
fYear
2008
fDate
April 27 2008-May 1 2008
Firstpage
181
Lastpage
186
Abstract
We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (open- via defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect. The flow is implemented using standard commercial tools for parameter extraction (PEX) and test generation (ATPG). A highly optimized branch-and bound algorithm to determine the values to be assigned to the aggressor lines is used to reduce both the ATPG efforts and the number of aborts. The resulting test sets are smaller and achieve a higher defect coverage than stuck-at n-detection test sets, and are robust against process variations.
Keywords
automatic test pattern generation; fault diagnosis; integrated circuit interconnections; aggressor-victim model; automatic test pattern generation; branch-and bound algorithm; interconnect open defects; open-via defects; parameter extraction; stuck-at n-detection test sets; Automatic test pattern generation; Automatic testing; Circuit faults; Computer architecture; Data mining; Failure analysis; Integrated circuit interconnections; Parameter extraction; Very large scale integration; Voltage; ATPG; Interconnect opens; Open-via defects;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location
San Diego, CA
ISSN
1093-0167
Print_ISBN
978-0-7695-3123-6
Type
conf
DOI
10.1109/VTS.2008.30
Filename
4511719
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