Title :
Accelerating manycore simulation by efficient NoC interconnection partition on FPGA simulation platform
Author :
Ku, Wei-Chun ; Chen, Tien-Fu
Author_Institution :
Nat. Chun Cheng Univ., Taiwan
Abstract :
Manycore architecture is the trend of system design. However, manycore simulators face the important issue than general multicore simulators is simulation speed. Several studies provide a FPGA simulation methodology to solve it, but they almost do it by providing a new internal design of core. And some of them don´t care the correctness without interconnection simulation. This paper provides a PVCT module and NIP methodology to solve these two issues. According to our experiment, we could provide a 91.4 MIPS simulation performance averagely with Splash2 benchmark by three physical cores. The number of three is decided by capability of Xilinx XC2V8000 FPGA chip.
Keywords :
field programmable gate arrays; integrated circuit interconnections; network-on-chip; FPGA simulation platform; MIPS simulation; NIP methodology; NoC interconnection; PVCT module; manycore simulation; multicore simulator; splash2 benchmark; Computer architecture; Context; Field programmable gate arrays; Hardware; Registers; Software; Switches;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-8500-0
DOI :
10.1109/VDAT.2011.5783638