An event-based VLSI network of integrate-and-fire neurons

Author

Chicca, Elisabetta ; Indiveri, Giacomo ; Douglas, Rodney J.

Author_Institution

Inst. of Informatics, Zurich Univ., Switzerland

Volume

5

fYear

2004

fDate

23-26 May 2004

Abstract

The growing interest in pulse-based neural networks is encouraging the development of hardware implementations of massively parallel, distributed networks of integrate-and-fire (I&F) neurons. We have developed a mixed-mode (analog/digital) VLSI device that comprises a reconfigurable network of I&F neurons and adaptive synapses. The synapses receive input spikes and the neurons transmit output spikes (events) using an asynchronous address-event representation (AER). We describe the network architecture, present experimental data demonstrating the characteristics of the single elements on the chip, and show that a competitive network configuration has winner-take-all (WTA) behaviour and produces spike synchronization.

Keywords

VLSI; asynchronous circuits; distributed parameter networks; mixed analogue-digital integrated circuits; network topology; neural nets; pulse shaping circuits; VLSI network; adaptive synapses; address-event representation; distributed networks; integrate-and-fire neurons; mixed-mode VLSI device; network architecture; neural networks; parallel networks; reconfigurable network; spike synchronization; winner-take-all behaviour; Circuits; Computer architecture; Computer networks; Fires; Network topology; Neural network hardware; Neural networks; Neurons; Pulse modulation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329536

Filename

1329536