An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI

Dynamic Voltage Scaling (DVS) is a successful design solution that addresses the challenges associated with low-power/energy and high-performance design in Deep Sub Micron (DSM) CMOS. In DSM, VLSI systems have become interconnect-centric; correspondingly, the associated design solutions should be adapted to preserve their functionality. In reference to this concern, and with respect to DVS, we propose a DVS scheme that takes interconnect effects into account. The proposed DVS scheme is a generalization of existing methods that treat systems as pure logic. To support this DVS scheme, two design metrics are introduced. These metrics model the performance of system components subject to DVS, based on the proportion of their delay due to interconnects. Based on the proposed design metrics, a compact delay model and a method for supply voltage selection are proposed. The limit of scaling for hazard-free system operation in VLSI systems is further formulated. It is shown that this limit can be smaller than the one dictated by the process technology. The proposed DVS scheme is applied to a 4-section global clock distribution network. Reported results show that this scheme improves both the timing accuracy and energy consumption aspects of DVS by 25% and 30% on average, respectively.