• DocumentCode
    3373636
  • Title

    Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation

  • Author

    Tadesse, D. ; Bahar, R.I. ; Grodstein, J.

  • Author_Institution
    Div. of Eng., Brown Univ., Providence, RI
  • fYear
    2008
  • fDate
    April 27 2008-May 1 2008
  • Firstpage
    339
  • Lastpage
    344
  • Abstract
    Speed debug is a critical part of microprocessor diagnosis and debug. During this stage, the test engineer must determine and increase the maximum speed at which the processor can run reliably. One of the difficulties of this stage is that the pass-fail boundary, in practice, is not abrupt, but rather encompasses a non-deterministic region of behavior. Accurately modeling this non-deterministic region is particularly important since it directly influences the amount of time needed for speed debug. Current chip debug efforts often rely on the use of brute force techniques to deduce the shape of the pass-fail boundary region. More specifically, speed debug (i.e., the process of finding and fixing critical paths that prevent a chip from running at a higher frequency) requires a thorough understanding of the width and shape of the pass-fail boundary region where the chip´s behavior is non- deterministic. In this paper, we propose a statistical method based on maximum likelihood estimation (MLE) techniques to infer the underlying shape of the non-deterministic region. Our method was tested on pre-production Intel microprocessors and was successful in modeling the shape of the fuzz-region in substantially fewer iterations compared to a brute force approach.
  • Keywords
    fault diagnosis; logic testing; maximum likelihood estimation; microprocessor chips; fast measurement; maximum likelihood estimation; microprocessor debug; microprocessor diagnosis; nondeterministic zone; speed debug; Circuit testing; Clocks; Frequency; Iris; Maximum likelihood estimation; Microprocessors; Reliability engineering; Shape; Velocity measurement; Very large scale integration; Maximum Likelihood Estimation; Microprocessor Diagnosis; Pass/Fail Region; Silicon Debug;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
  • Conference_Location
    San Diego, CA
  • ISSN
    1093-0167
  • Print_ISBN
    978-0-7695-3123-6
  • Type

    conf

  • DOI
    10.1109/VTS.2008.18
  • Filename
    4511747