A General Failure Candidate Ranking Framework for Silicon Debug

In advanced nanometer designs, various electrical effects could introduce unexpected circuit delays and lead to performance failures. Although electrically induced timing errors could be detected by applying delay testing, tools for debugging this type of error are still not widely adopted. We propose a general silicon debug framework which focuses on diagnosing silicon electrical bugs under functional test patterns. In this paper, we present FCR (Failure Candidate Ranker) which is one of the key components of the proposed framework. FCR employs various reasoning techniques including backward active/trigger tracing and forward symptom matching. We´ll apply FCR to several industrial cases and show the effectiveness of identifying the error sources.