DocumentCode
3373729
Title
Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms
Author
Lisboa, C.A. ; Argyrides, C. ; Pradhan, D.K. ; Carro, L.
Author_Institution
Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre
fYear
2008
fDate
April 27 2008-May 1 2008
Firstpage
363
Lastpage
370
Abstract
For technologies beyond the 45 nm node, radiation induced transients will last longer than one clock cycle. In this scenario, temporal redundancy techniques will no longer be able to cope with radiation induced soft errors, while spatial redundancy techniques still impose high power and area overheads. The solution to this impasse is the use of algorithm level techniques, able to detect and correct errors with low cost. In this paper, a new approach to deal with this problem is proposed, and applied to matrix multiplication algorithm. The proposed technique is compared to previously published fault tolerance techniques, and the costs of detection and recomputation for both approaches are compared and discussed.
Keywords
fault tolerance; matrix multiplication; radiation effects; transients; fault tolerance; matrix multiplication algorithms; radiation induced transient faults; soft errors; CMOS technology; Computational efficiency; Costs; Error correction; Fault detection; Fault tolerance; Pulse circuits; Redundancy; Testing; Very large scale integration; fault tolerance; long transients; radiation effects; recomputation granularity;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location
San Diego, CA
ISSN
1093-0167
Print_ISBN
978-0-7695-3123-6
Type
conf
DOI
10.1109/VTS.2008.29
Filename
4511752
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