Title :
Degradation of breakdown voltage of DMOS due to arsenic implant damage
Author :
Shibib, M. Ayman ; Siket, J.M. ; Tse, P.K. ; Hsieh, C.-M.
Author_Institution :
AT&T Bell Labs., Reading, PA, USA
Abstract :
We report the observation and detailed study of the degradation of breakdown voltage for a double-diffused power MOSFET (DMOS) in relation to the process of high dose arsenic implantation. We established a direct link between the breakdown voltage degradation and the dose and process conditions of the formation of the DMOS source. Starting from the observed electrical characteristics, we identified the particular cell site that exhibited the leakage by thermal imaging. Then, detailed silicon defect etching was performed on devices which showed leakage characteristics. We report, for the first time, the direct association of a double pit defect with the site of breakdown voltage degradation on numerous devices that exhibited the low breakdown voltage. We demonstrated that the conditions of the source implant have a direct influence on the formation of these defects, and we established a physical model of the interaction of the defect site with the spread of the depletion layer. Based on this model, we demonstrated experimentally that we can obtain devices with high breakdown voltages despite these defects. Additionally, the defects could be avoided by lowering the arsenic implant dose
Keywords :
BIMOS integrated circuits; arsenic; electric breakdown; etching; infrared imaging; ion implantation; leakage currents; power MOSFET; power integrated circuits; semiconductor device reliability; semiconductor device testing; semiconductor process modelling; DMOS source formation; SiO2-Si:As; arsenic implant damage; arsenic implant dose; breakdown voltage; breakdown voltage degradation; cell site leakage; defect formation; defect site; defect site-depletion layer spread interaction model; depletion layer; double pit defect; double-diffused power MOSFET; electrical characteristics; high dose arsenic implantation; leakage characteristics; physical model; power DMOSFET; process conditions; silicon defect etching; source implant conditions; thermal imaging; Breakdown voltage; CMOS technology; Electric variables; Etching; FETs; Heat treatment; Microelectronic implants; Silicon; Thermal degradation; Voltage measurement;
Conference_Titel :
Power Semiconductor Devices and ICs, 1998. ISPSD 98. Proceedings of the 10th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-4752-8
DOI :
10.1109/ISPSD.1998.702705