Log-Domain Time-Multiplexed Realization of Dynamical Conductance-Based Synapses

We present a compact circuit architecture for analog VLSI realization of event-addressable neuromorphic arrays with conductance-based synaptic dynamics. Synaptic input events are time-multiplexed, pooled by synapse type according to common reversal potential and activation dynamics. One such physical synapse element per postsynaptic neuron is provided for each type, selected by type index along with postsynaptic address. A log-domain encoding of first-order linear dynamics of synaptic conductance results in a compact circuit realization with three MOS transistors per synapse element. Circuit simulations show low-power operation with linear dynamics in conductance.