Low-Power 4-b 2.5 GSPS Pipelined Flash Analog-to-Digital Converters in 0.13 μm CMOS

This paper presents a 4-bit high-speed, low-power, pipelined flash analog-to-digital converter (ADC). The proposed ADC is pipelined and mainly consists of three stages: 1) track-and-hold (T/H), 2) differential comparator, and 3) Differential Cascode Voltage Switch with Pass Gates (DCVSPG) encoder. The T/H uses a current mode, dual-array structure to reduce the aperture jitter for high input frequency. The differential comparator eliminates the use of the resistor ladder circuit by generating the reference voltages internally. The DCVSPG encoder has a full output signal swing and compact logic design style of pass gate circuits which makes it suitable for high sampling frequency. The DCVSPG encoder reduces the power consumption by a factor of 88% as compared to the conventional ROM encoder. The ADC is designed in 130 nanometer CMOS technology. FFT tests prove proper operation of the ADC sampled at 2.5 GHz for input signal frequency up to 1 GHz