The design cube-a model for VHDL designflow representation

Hardware design under the use of the VHSIC hardware description language (VHDL) has to consider three independent property scales that influence the design process from an abstract level to gate level, namely, the design view, the timing aspect, and the value representation. The well-known Y-chart model is not suitable to describe these property scales in a satisfactory way. A new model for the design flow representation with the particular view on VHDL is presented. It is a three-dimensional cube with three coordinates divisions per dimension. Each state of the cube represents a modeling style in VHDL. For the use of more powerful hardware description languages, the cube may be extended to four coordinates per dimension