DocumentCode
3374180
Title
Selected aspects of component modeling
Author
Pawlack, A.
Author_Institution
GMD/SET, St. Augustin
fYear
1992
fDate
7-10 Sep 1992
Firstpage
683
Abstract
Summary form only given. VHSIC hardware description language (VHDL) models should be defined along precise guidelines in order to guarantee their compatibility and efficiency. The author reports on the generation of component models and the quantitative analysis of models
Keywords
circuit CAD; specification languages; VHDL; VHSIC hardware description language; compatibility; component modeling; efficiency; quantitative analysis; Code standards; Costs; Databases; Electrical capacitance tomography; Libraries; Q factor; Robustness; Standards development; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location
Hamburg
Print_ISBN
0-8186-2780-8
Type
conf
DOI
10.1109/EURDAC.1992.246192
Filename
246192
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