Title :
A high throughput VLSI design with hybrid memory architecture for H.264/AVC CABAC decoder
Author :
Liao, Yuan-Hsin ; Li, Gwo-Long ; Chang, Tian-Sheuan
Author_Institution :
Graduated Inst. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
fDate :
May 30 2010-June 2 2010
Abstract :
A high throughput context-based adaptive binary arithmetic coding (CABAC) decoding design with hybrid memory architecture for H.264/AVC is presented in this paper. To accelerate the decoding speed with hardware cost consideration, a new hybrid memory two-symbol parallel decoding technique is proposed. In addition, an efficient mathematical transform method is also proposed to further decrease the critical path of two-symbol binary arithmetic decoding procedure. The proposed architecture is implemented by UMC 90nm technology and experimental results show that our proposal can operate at 264 MHz with 42.37k gate count, and the throughput is 483.1 Mbins/sec, which surpasses previous design with 48.6% hardware cost saving.
Keywords :
VLSI; codecs; nanotechnology; video coding; H.264/AVC CABAC decoder; VLSI design; context-based adaptive binary arithmetic coding decoding design; frequency 264 MHz; hybrid memory architecture; hybrid memory two-symbol parallel decoding technique; mathematical transform method; size 90 nm; two-symbol binary arithmetic decoding procedure; Acceleration; Arithmetic; Automatic voltage control; Costs; Decoding; Hardware; Memory architecture; Proposals; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537137