Title :
Synchronous design in VHDL
Author :
Debreil, Alain ; Oddo, Philippe
Author_Institution :
Bull S.A., Les Clayes-sous-Bois, France
Abstract :
VHSIC hardware description language (VHDL) is a very rich and flexible language, which offers large possibilities in the simulation domain. The current state of the art of the formal proof technique does not enable handling all these possibilities. It applies only to synchronous descriptions. The author proposes definitions of the main object semantics to be used in a synchronous description. The resulting VHDL guidelines are described. These make up the bases of a VHDL subset suitable for formal proof and also for synthesis tools
Keywords :
circuit CAD; formal verification; specification languages; VHDL; VHSIC hardware description language; formal proof technique; object semantics; simulation domain; synthesis tools; Clocks; Design methodology; Guidelines; Hardware; Latches; Logic circuits; Registers; Standardization; Synchronization; Timing;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246194
