DocumentCode :
3374260
Title :
New spider-webs test structure and characterization methodology for flash memory tunnel oxide quality
Author :
Fan, T.H. ; Lu, T.C. ; Pan, Sam
Author_Institution :
Special Device / Modeling Dept., & Silicon Lab, Macronix Int. Co, Hsinchu, Taiwan
fYear :
2002
fDate :
8-11 April 2002
Firstpage :
133
Lastpage :
137
Abstract :
Tunnel oxide quality is a key parameter during flash memory development. A high quality tunnel oxide will result in good cell endurance characteristics. However, the conventional tunnel oxide characterization is usually based on a large area capacitor test structure with a high sheet resistance floating poly-silicon gate, and, as a result, an over-estimated oxide quality is obtained. In this study, we design a new test structure and a new characterization methodology for tunnel oxide measurement. It is found that more accurate and reliable tunnel oxide lifetime prediction can be obtained with this new approach. Besides, this measurement is correlated to flash memory endurance performance.
Keywords :
flash memories; integrated circuit reliability; integrated circuit testing; semiconductor device breakdown; tunnelling; TDDB distribution; accelerated reliability tests; cell endurance characteristics; characterization methodology; flash memory tunnel oxide quality; large area capacitor test structure; spider-webs test structure; tunnel oxide lifetime prediction; Area measurement; Capacitors; Contact resistance; Current measurement; Electrical resistance measurement; Flash memory; Life testing; Nonvolatile memory; Tunneling; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 2002. ICMTS 2002. Proceedings of the 2002 International Conference on
Print_ISBN :
0-7803-7464-9
Type :
conf
DOI :
10.1109/ICMTS.2002.1193185
Filename :
1193185
Link To Document :
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