DocumentCode :
3374326
Title :
New design error modeling and metrics for design validation
Author :
Kang, Sungho ; Szygenda, Stephen A.
Author_Institution :
Comput. Eng. Res. Center, Austin, TX, USA
fYear :
1992
fDate :
7-10 Sep 1992
Firstpage :
472
Lastpage :
477
Abstract :
When simulation is used for design verification, a subset of simulation input patterns is used, since exhaustive simulation is usually not practical. This produces uncertainty as to how much of the design has been verified. To provide a measure of the simulation pattern coverage based on design error modeling, a new simulation coverage metric is introduced. This measure is useful for obtaining insight into the actual level of design validation, since it provides more realistic results than those which are presently available
Keywords :
logic design; logic testing; design error modeling; design validation; design verification; metrics; simulation input patterns; Automatic test pattern generation; Automatic testing; Circuits; Computational modeling; Computer errors; Computer simulation; Design engineering; Digital systems; Drives; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
Type :
conf
DOI :
10.1109/EURDAC.1992.246201
Filename :
246201
Link To Document :
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