Title :
Design for testability view on placement and routing
Author :
Feltham, Derek ; Khare, Jitendra ; Maly, Wojciech
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
It is demonstrated that there is a relationship between the topology of the layout of the designed IC and the quality of testing. Based on this relationship, a testability cost function is developed for automated layout generation. The presented example indicates that a decrease in the testability objective function does correspond to an increase in the quality of testing without any penalty in terms of the cost of test generation. It is envisioned that such a function can be added as a component to the total objective function used by a modern placement and routing algorithm. Thus, using the presented techiques, it is possible to significantly improve the testability of a given circuit without increasing the cost of test generation
Keywords :
VLSI; circuit layout CAD; design for testability; integrated circuit testing; VLSI circuits; automated layout generation; design for testability; layout topology; placement; quality of testing; routing; testability cost function; Automatic testing; Circuit faults; Circuit testing; Costs; Design for testability; Electrical fault detection; Fault detection; Integrated circuit testing; Manufacturing; Routing;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246215
